 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a APPLICATIONS Security Coprocessor for High Speed Networking Products (Routers, Switches, Hubs) Cryptographic Core for Firewalls, Hardware Encryptors, and More Crypto Peripheral for Implementing Secure NIC Adapters (10/100 Ethernet, Token Ring, ISDN) Secure Modem-on-a-Chip (V.34, ADSL) FEATURES DES CRYPTO BLOCK 640 Mbps Sustained Performance--Single DES 214 Mbps Sustained Performance--Triple DES Supports All Modes: ECB; CBC; 64-Bit OFB; and 1-, 8-, 64-Bit CFB. Includes Automatic Padding Implements IPsec ESP Transforms Autonomously at OC-3 (155 Mbps) Rates (3-DES, SHA-1) HASH BLOCK Hardware-Based SHA-1 and MD-5 Hashing 253 Mbps Sustained Performance--SHA-1 315 Mbps Sustained Performance--MD-5 Implements IPsec AH and HMAC Transforms R DSP ADSP-2141L SECURE KERNEL CONTROL Tamper-Resistant Isolation of Cryptographic Functions Enforces Security Perimeter Around Crypto Functions and Crypto Storage Locations Anticloning Protection Secure Algorithm Download SafeNet CGX LIBRARY On-Chip SafeNet CGX Crypto Library with Flexible CGX API Includes Chained and Parallel Execution Commands Such as Hash-and-Encrypt Embodied as 32K Words (32K 24) Kernel Program Mask-Programmed into On-Chip ROM On-Chip Protected 4K 16 Security Scratchpad RAM RANDOM NUMBER GENERATOR Hardware-Based Nondeterministic Random Number Generator Generates Internal Session Keys That Are Never Exposed Outside of the SafeNet DSP Redundant Fail-Safe Design Up to 1.3 Mbits of Random Data Available per Second FUNCTIONAL BLOCK DIAGRAM KERNEL MODE CONTROL BUS_MODE IDMA MODE INTERRUPTS FLAGS IDMA BUS 16 IDMA INTERFACE 16 ADSP-218x DSP CORE 16OR 32-BIT BUS PCI MODE DMA-32 CONTROLLER 32 PCI OR CARDBUS INTERFACE 32 SPORT 0 SERIAL PORTS SPORT 1 KERNEL ROM 32K 24 PROG ROM 16K 24 DATA ROM 16K 16 TIMER PROTECTED KERNEL RAM (4K 16) ENCRYPT BLOCK (DES, 3-DES) HASH BLOCK (MD-5, SHA-1) RNG BLOCK PUBLIC KEY ACCELERATOR BUS_MODE EMI BUS INTERRUPT CONTROLLER APPLICATION REGISTERS EXTERNAL MEMORY INTERFACE 32-BITS DATA LASER VARIABLE STORE SERIAL EEPROM INTERFACE BUS_SEL 26-BITS ADDR PF7/INT_H RAM/ROM SafeNet is a registered trademark of Information Resource Engineering (IRE). REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 ADSP-2141L PUBLIC KEY ACCELERATOR Accelerator for Math-Intensive Public Key Operations Diffie-Hellman Negotiate: <29 ms (1024-Bit Modulus, 180-Bit Exponent) RSA 1024-Bit Sign: <29 ms; RSA 1024-Bit Verify: 6 ms DSA Sign: <39 ms; DSA Verify: <66 ms KEY MANAGEMENT BLOCK Laser-Programmed Unique Triple-DES Cryptovariable Protects Off-Chip Storage Support for Secure Storage of Both Secret Keys and Public/Private Key Pairs Trust-Model Rules Enforcement Only Encrypted Keys May Be Exported Off the Chip Internal Key Cache for 15 Keys--Can Be Expanded to 700 Keys On-Chip Keys May Also Be Securely Stored Off-Chip, Allowing Unlimited Storage DSP CORE 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch Zero-Overhead Looping Low Power Dissipation 16K Words (16K 24) On-Chip Program RAM 16K Words (16K 16) On-Chip Data RAM 64M Words Off-Chip Program and Data Memory Programmable 16-Bit Interval Timer with Prescale PCI BUS/CARDBUS INTERFACE 32-Bit 3.3 V Bus Interface 33 MHz or 40 MHz* Bus Speed Bus Master and Target Modes Can Directly DMA Between Crypto Functions and Other PCI Bus Agents *66 MHz speed pending chip characterization. GENERAL DESCRIPTION The ADSP-2141L SafeNet DSP is a highly integrated embedded security processor that incorporates a sophisticated, general purpose DSP, along with a number of high performance Cryptographic function blocks, as well as PCI, DMA and Serial EEPROM interfaces. It is fabricated in 0.35 CMOS triplelayer metal technology and uses a 3.3 V power supply. It is available in a 208-lead MQFP package with a commercial (0C to 70C) temperature range. DSP Core The DSP is a standard Analog Devices ADSP-218x core with full ADSP-2100 family compatibility. The ADSP-218x Core combines the base DSP components from the ADSP-2100 family with the addition of two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The external memory interface of the 218x core has been extended to support up to 64M-words addressing for both program and data memory. Some core enhancements have been added in the ADSP-2141L, including on-chip security ROM and interrupt functions. Refer to the Analog Devices ADSP-2183 data sheet for further information. SafeNet CGX Library-Secure Kernel The SafeNet CGX Library is a crypto library embodied as firmware (a secure kernel) that is mask-programmed into ROM within the DSP. This solution protects the library from tampering. The CGX Library provides the Application Programming Interface (API) to applications that require security services from the ADSP-2141L. Those applications may be software executing in user mode on the DSP, or they may be external host software accessing the ADSP-2141L via a PCI bus. Approximately 40 Crypto commands--called CGX (CryptoGraphic eXtensions)-- are provided at the API and a simple control block structure is used to pass arguments into the secure kernel and return status. The CGX library includes integrated drivers for the various hardware crypto blocks on the chip. This allows the programmer to ignore those details and concentrate on other product design issues. The CGX library firmware runs under a protected mode state of the DSP as described in the Kernel Mode Control section following. This guarantees the security integrity of the system during the execution of CGX processes and, for example, prevents disclosure of cryptographic key data or tampering with a security operation. Kernel Mode Control The Kernel Mode Control subsystem is responsible for enforcing the security perimeter around the cryptographic functions of the ADSP-2141L. The device may operate in either user mode (kernel space is not accessible) or kernel mode (kernel space is accessible) at a given time. When in kernel mode, the kernel RAM and certain protected crypto registers and functions (kernel space) are accessible only to the CGX library firmware. The CGX Library executes host-requested macro-level functions and then returns control to the calling application. The kernel mode control subsystem resets the DSP should any security violation occur, such as attempting to access a protected memory location while in user mode. -2- REV. 0 ADSP-2141L The 4K x 16 kernel RAM provides a secure storage area on the ADSP-2141L for sensitive data such as keys or intermediate calculations during public key operations. The Kernel Mode Control subsystem (above) enforces the protection by allowing only internal secure kernel mode access to this RAM. A public keyset and a cache of up to 15 secret keys may be stored in kernel RAM. Secure key storage may be expanded to 700 secret keys by assigning segments of the DSP's internal data RAM to be protected. Furthermore, a virtually unlimited number of data encryption keys may be stored in an encrypted form in off-chip memory. Encrypt Block Protected Kernel RAM PCI/Cardbus Interface A full 40 MHz/33 MHz PCI bus interface has been added to the core DSP functions. The 32-bit PCI interface supports both bus master and target modes. The ADSP-2141L is capable of using DMA to directly access data on other PCI entities and pass that data through its encryption/hash engines. 32-Bit DMA Controller The encrypt block performs high speed DES and Triple-DES encrypt/decrypt operations. All four standard modes of DES are supported: Electronic Code Book (ECB), Cipher Block Chaining (CBC), 64-bit Output Feedback (OFB) and 1-bit, 8-bit and 64bit Cipher Feedback (CFB). The DES encrypt/decrypt operations are highly pipelined and execute full 16-round DES in only four clock cycles. Hardware support for padding insertion, verification and removal further accelerates the encryption operation. Context switching is provided to minimize the overhead of changing crypto keys and Initialization Vectors (IVs) to nearly zero. Hash Block The ADSP-2141L incorporates a high performance 32-bit DMA controller which can be set up to move data efficiently between Host PCI memory, the hash/encrypt blocks, and/or external memory. The DMA controller can be used with the PCI bus in master mode, thus autonomously moving 32-bit data with minimal DSP intervention. Up to 255 long words (1020 bytes) can be moved in a burst at up to 160 Mbytes per second. Application Registers The application registers are a set of memory-mapped registers that facilitate communications between the ADSP-2141L and a host processor via the PCI bus. One of the registers is a mailbox that is 44 bytes long and set up to hold the CGX command structure passed between the host and DSP processors. The application registers also provide the mechanism that allows the DSP and the external host to negotiate ownership of the hash/ encrypt block. Serial EEPROM Interface The secure hash block is tightly coupled with the encrypt block and provides hardware accelerated one-way hash functions. Both the MD-5 and SHA-1 algorithms are supported. Combined operations that chain both hashing and encrypt/decrypt functions are provided in order to significantly reduce the processing time for data that needs both operations applied. For hash-then-encrypt and hash-then-decrypt operations, the ADSP-2141L can perform parallel execution of both functions from the same source and destination buffers. For encrypt-then-hash and decrypt-then-hash operations, the processing must be sequential, but minimum latency is still provided through the pipeline chaining design. An offset may be specified between the start of hashing and the start of encryption to support certain protocols such as IPsec. A `mutable bit handler' is also provided on the hash engine to facilitate IPsec AH processing. Random Number Generator (RNG) Block The serial EEPROM interface allows an external nonvolatile memory to be connected to the ADSP-2141L for storing PCI configuration information (Plug and Play), as well as generalpurpose nonvolatile storage. For example, encrypted (black) keys could be stored into EEPROM for fast recovery after a power outage. Interrupt Controller The DSP core provides support for 14 interrupt sources, including six external and eight internal. All interrupts are prioritized into 12 levels and interrupt nesting may be enabled or disabled under software control. The security block interrupt controller provides enhancements to the DSP interrupt functions. Primarily, the interrupt controller provides a new interrupt generation capability to the DSP or to an external host processor. Under programmable configuration control, a crypto interrupt may be generated due to completion of certain operations such as encrypt complete, hash complete. The interrupt may either be directed at the DSP core (on IRQ2), or provided on an output line (PF7/INT_H) to a host subsystem. Laser Variable Storage The hardware random number generator provides a true, nondeterministic noise source for the purpose of generating keys, Initialization Vectors (IVs), and other random number requirements. Random numbers are provided as 16-bit words to the kernel. The CGX kernel requests random numbers as needed to perform requested CGX commands such as CGX_Gen_Key, and can also directly supply from 1 to 65,535 random bytes to a host application via the CGX_Random command. Public Key Accelerator The public key accelerator module works in concert with the CGX kernel firmware to provide full public key services to the host application. The kernel provides macro-level functions to perform Diffie-Hellman key agreement, RSA encrypt or decrypt, DSA compute and verify digital signatures. The hardware accelerator block speeds computation-intensive operations such as large vector multiply, add, subtract, square. The laser variable storage consists of 256 bits of tamper-proof factory-programmed data that is only accessible to the internal function blocks and the security kernel. Included in these laser variable bits are: * Local Storage Variable (master key-encryption key) * Randomizer Seed (to supplement the true entropy fed into the RNG) * Program Control Data (enables/disables various features and configures the ADSP-2141L) * CRC of the Laser Data (to verify laser data integrity). REV. 0 -3- ADSP-2141L The Program Control Data Bits (PCDBs) include configuration for permitted key lengths, algorithm enables, Red KEK loading. Most of the PCDB settings may be overridden with a digitally signed token which may be loaded into the ADSP-2141L when it boots. These tokens are created by IRE and each is targeted to a specific ADSP-2141L using a hash of its unique identity. Downloadable Secure Code ARCHITECTURE OVERVIEW This section provides an architecture-level description of the unique function blocks within the ADSP-2141L. Memory Map The ADSP-2141L allows additional security functions to be added to the device through a secure download feature. Up to 16K words of code may be downloaded into internal memory within the DSP and this code can be given the security privileges of the CGX kernel firmware. All downloaded firmware is authenticated with a digital signature and verified with an on-chip public key. Additional functions could include new encryption, hash or public key algorithms such as IDEA, RC-4, RIPEMD, elliptic curve, or any other application that needs direct control over the protected cryptographic hardware. The ADSP-2141L memory map is very similar to that of the ADSP-2183 DSP, except that it includes significantly more offchip memory addressing, and has additional crypto registers which are accessible to the user. DSP Core The DSP core is architecturally identical to the ADSP-218x with a few exceptions. * The memory map includes additional external memory addressing through the PMOVLAY and DMOVLAY mechanisms. For more information, see the Memory Map section. * Additional memory-mapped crypto registers are available in the kernel data RAM space. * The PF7/INT_H flag pin may be reassigned to be the host interrupt output. 0x3FFF 0x2000 8K KERNEL TOP KERNEL MODE (PMOVLAYL = C) (PMOVLAYH = 000) 8K KERNEL BASE KERNEL MODE (PMOVLAYL = F) (PMOVLAYH = 000) 0x1FFF 8K INTERNAL PAGE (PMOVLAYL = 0) (PMOVLAYH = 000) 8K EXTERNAL PAGE = 0 (PMOVLAYL = 1) (PMOVLAYH = 000) 8K EXTERNAL PAGE 1 (PMOVLAYL = 2) (PMOVLAYH = 000) 8K KERNEL PAGE 8191 (PMOVLAYL = 2) (PMOVLAYH = FFF) PMOVLAYL = LS NIBBLE OF PMOVLAY PMOVLAYH = MS 3 NIBBLES OF PMOVLAY SHADED = KERNEL SPACE 0x0000 8K INTERNAL (COMMON BANK) UP TO 64 MEGAWORDS EXTERNAL PROGRAM MEMORY (PMOVLAYL ALTERNATES 2, 1, 2, 1...) Figure 1. Program Memory (MMAP = 0) 0x3FFF 0x2000 8K KERNEL TOP KERNEL MODE (PMOVLAYL = C) (PMOVLAYH = 000) 8K KERNEL KERNEL MODE (PMOVLAYL = D) (PMOVLAYH = 000) 8K KERNEL KERNEL MODE (PMOVLAYL = E) (PMOVLAYH = 000) 8K KERNEL KERNEL MODE (PMOVLAYL = F) (PMOVLAYH = 000) 0x1FFF 8K INTERNAL (PMOVLAYL = 0) (PMOVLAYH = 000) PMOVLAYL = LS NIBBLE OF PMOVLAY PMOVLAYH = MS 3 NIBBLES OF PMOVLAY SHADED = KERNEL SPACE 8K EXTERNAL 0x0000 Figure 2. Program Memory (MMAP = 1) 0x3FFF 0x3FE0 0x3FDF 0x2000 0x1FFF 0x1800 0x17FF 0x1000 0x0FFF 0x0000 32 MEMORY-MAPPED REGISTERS 8160 WORDS INTERNAL UP TO 64 MEGAWORDS EXTERNAL DATA MEMORY (DMOVLAYL ALTERNATES 2, 1, 2, 1...) MEMORY-MAPPED REGISTERS 8K INTERNAL PROTECTED (DMOVLAYL = 0) 4K KERNEL RAM (DMOVLAYH = 000) (DMOVLAY = 000F) KERNEL MODE 8K EXTERNAL PAGE = 0 (DMOVLAYL = 1) (DMOVLAYH = 000) 8K EXTERNAL PAGE 1 (DMOVLAYL = 2) (DMOVLAYH = 000) 8K KERNEL PAGE 8191 (DMOVLAYL = 2) (DMOVLAYH = FFF) SHADED = KERNEL SPACE Figure 3. Data Memory -4- REV. 0 ADSP-2141L * IRQ2 now can include interrupt sources from the crypto subsystem, depending on interrupt mask registers. * A new read register has been added to indicate the state of interrupt enable and interrupt masks. * The kernel mode control subsystem has been added to supervise the protected mode of operation of the DSP core. * Internal RAM protection logic has been added to allow the kernel to seize increments of 1K word of internal PRAM and DRAM. * Bus mode configuration (218x vs. PCI) pins have been added. * 32K words of kernel program ROM have been added to the DSP memory space. (See the Memory Map section.) Kernel Mode Control set to 0x000F. Once in kernel mode, any branch to nonkernel space program memory causes the DSP to return to user mode. (Note: For security reasons when in kernel mode, the DSP does not respond to Emulator bus requests.) The kernel mode can be interrupted during execution; however, during certain periods where sensitive data is being moved, all interrupts are disabled. Within the interrupt service routine, another call to the kernel (CGX call) may be made if desired, although there are limitations on which CGX commands may preempt another. (For information, see the ADSP-2141L CGX Interface Programmer's Guide http://www.ire-ma.com/proddoc.htm.) Only one level of kernel mode nesting is permitted. An interrupt to a user mode vector location while in nested kernel mode will also trigger the violation reset logic. Once the interrupt service routine is finished, the return-frominterrupt must return control back to the kernel at the address/ overlay that was originally interrupted, otherwise the protection logic will issue a chip reset. Hash and Encrypt Block Overview The kernel mode control subsystem provides the following functions which serve to enforce the security integrity of the ADSP-2141L: * Provide a means to securely enter the kernel mode. * Provide a means to properly exit the kernel mode. * Prevent user mode access to protected memory and register locations. * Manage interrupts during kernel mode executions. * Manage the reset function to ensure that sensitive variables in DSP registers are erased. Most of the kernel mode control functions are implemented in the hardware of the ADSP-2141L and are not directly visible to nonkernel applications (user mode). Any attempt by a user mode application program running on the DSP to access a kernel space addresses (PRAM 0x2001 - 0x3FFF, PMOVLAY 000C - 000F; or DRAM 0x0000 - 0x17FF, DMOVLAY 000F) results in an immediate chip reset and all sensitive registers and memory locations are erased. Kernel mode may only be entered via a call, jump or increment to address 0x2000 with PMOVLAY REGISTER ADDRESS 7 The encrypt block is tightly coupled to the hash block in the ADSP-2141L and therefore the two are discussed together. Refer to Figure 4, Hash/Encrypt Functional Block Diagram, for the following description. The algorithms implemented in the combined hash and encryption block are: DES, Triple DES, MD-5 and SHA-1. Data can be transferred to and from the module once to perform both hashing and encryption on the same data stream. The DES encrypt/decrypt operations are highly paralleled and pipelined, and execute full 16-round DES in only four clock cycles. The internal data flow and buffering allows parallel execution of hashing and encryption where possible, and allows processing of data concurrently with I/O of previous and subsequent blocks. WR RD PAD INSERTION 512-BIT FIFO PAD CONSUME AND VERIFY DSP OR PCI WRITE CONTEXT 512-BIT FIFO 16-/32-BIT INPUT BUS ENCRYPT/ DECRYPT BLOCK DSP OR PCI READ CONTEXT CONTEXT STORAGE (0/1) 16-/32-BIT OUTPUT BUS HASH DIGEST HASH BLOCK MUTABLE BIT PROCESSING PAD INSERTION (ENCRYPT-THEN-HASH) (DECRYPT-THEN-HASH) Figure 4. Hash/Encrypt Functional Block Diagram REV. 0 -5- ADSP-2141L Context switching is optimized to minimize the overhead of changing cryptographic keys to near zero. The software interface to the module consists of a set of memory-mapped registers, all of which are visible to the DSP and most of which can be enabled for host access via the PCI bus. A set of five, 16-bit registers define the operation to be performed, the length of the data buffer to be processed, in bytes, the offset between the start of hashing and encryption (or vice versa), and the padding operation. If the data length is unknown at the time the encrypt/decrypt operation is started, the data length register may be set to zero, which specifies special handling. In this case, data may be passed to the hash/encrypt block indefinitely until the end of data is encountered. At that time, the operation is terminated by writing a new control word to the hash/encrypt control register (either to process the next packet or to invoke the idle state if there is no further work to do). This will close out the processing for the packet, including the addition of the selected crypto padding. A set of seven status registers provides information on when a new operation can be started, when there is space available to accept new data, when there is data available to be read out, and the results from the padding operation. Crypto Contexts with trailing pad length and next header byte (for IPsec), or fixed character padding. Note that for the IPsec and PKCS#7 pad protocols, there are cases where the padding not only fills out the last 8-byte block, but also causes an additional 8-byte block of padding to be added. For the hash operations, padding is automatically added as specified in the MD-5 and SHA-1 standards. When the hash final command is issued indicating the last of the input data, the algorithm-specified padding and data count bits are added to the end of the hash input buffer prior to computing the hash. Data Offsets Certain security protocols, including IPsec, require portions of a data packet to be hashed while the remainder of the data is both hashed and encrypted. The ADSP-2141L supports this requirement through the OFFSET register, which allows specifying the number of 32-bit dwords of offset between the hash and encrypt/ decrypt operations. Black Key Loads There are two sets of crypto-context registers. Each context contains a DES or triple DES key, initialization vector, and precomputed hashes (inner and outer) of the authentication key for HMAC operations. The contexts also contain registers to reload the byte count from a previous operation (which is part of the hashing context), as well as an IV (also called salt) for decrypting a black key, if necessary. Once a crypto-context has been loaded and the operation defined, data is processed by writing it to a data input FIFO. At the I/O interface, data is always written to, or read from, the same address. Internally, the hash and encryption functions have separate 512-bit FIFOs, each with their own FIFO management pointers. Incoming data is automatically routed to one or both of these FIFOs, depending on the operation in progress. Output from the encryption block is read from the data output FIFO. In encrypt-hash or decrypt-hash operations, the data is also automatically passed to the hashing data input FIFO. Output from the hash function is always read from the digest register of the appropriate crypto-context. The initialization vector to be used for a crypto operation can be loaded as part of a crypto-context. When an operation is complete, the same context will contain the resulting IV produced at the end, which can be saved away and restored later to continue the operation with more data. In certain packet-based applications such as IPsec, a feature is available that avoids the need for the control software to generate and load random IVs for outgoing (encrypted) packets. Effectively, the IV register can be configured to be automatically updated with new random numbers for each encrypted packet, with almost no software intervention. Padding The cryptographic keys loaded as part of a crypto-context can be stored off-chip in a black, or encrypted, form. If the appropriate control bit is set (HECNTL Bit 15), the DES or 3-DES key will be decrypted immediately after it is written into the context register. The hardware handles this decryption automatically. The Key Encryption Key (KEK) that covers the black keys is loaded in a dedicated write-only KEK register within the ADSP-2141L. The IV for decrypting the black secret key is called `salt' and must be stored along with the black key (as part of the context). Note that 3-DES CBC mode is used for protecting 3-DES black keys and single DES CBC is used for single DES black keys. When black keys are used, the key-decrypt operation adds a 6-cycle overhead (0.15 s @ 40 MHz) for DES keys or 36-cycle overhead (0.9 s @ 40 MHz) for triple DES keys each time a new crypto-context is loaded. (Note that if the same context is used for more than one packet operation, the key decryption does not need to be performed again.) Depending on the sequencing of operations, this key decryption may in fact be hidden (from a performance impact perspective) if other operations are underway. This is because the black key decryption process only requires that the DES hardware be available. For example, if the DSP is reading the previous hash result from the output FIFO, the black key decryption can be going on in parallel. Also note that the data driver firmware does NOT have to wait for the key to be decrypted before writing data to the input FIFO. The hardware automatically waits for the key to be decrypted before beginning to process data for a given packet. So, with efficient pipeline programming, it is possible to make the impact of black key essentially zero. The KEK for key decryption is loaded via the secure kernel firmware using one of the CGX key manipulation commands. (For more information, see the Command Summary section.) This KEK is typically the same for all black keys, since it is usually protecting local storage only. It is designated the DKEK in the CGX API. One of the laser-programmed configuration bits specifies whether red (plaintext) keys are allowed to be loaded into the ADSP2141L from a host. If the AllowRedKeyLoad laser bit is not set, keys may only be loaded in their black form. This is useful in systems where export restrictions limit the key length that may be used or where the external storage environment is untrusted. -6- REV. 0 When the input data is not a multiple of eight bytes (a 64-bit DES block), the encrypt module can be configured to automatically append pad bytes. There are several options for how the padding is constructed, which are specified using the pad control word of the operation description. Options include zero padding, pad-length character padding (PKCS#7), incrementing count, ADSP-2141L If the AllowRedKeyLoad bit is set, keys may be loaded either in their black form, or in the red or unencrypted form. Note that the laser configuration bit may be overridden with a signed enabler token. (For more information, see the Laser Variable Storage section.) Depending on the definition of the security module boundary in a given application, FIPS 140-1 may require the use of black keys to protect key material. In other words, if the security boundary does not enclose the database where keys are stored, those keys must be protected from compromise. Black key is a satisfactory way to meet this FIPS requirement. Random Number Generator (RNG) Block result, as well as specifying the length and operation type. Once the operation type field is written, the processor polls the operation complete status while the calculation is carried out. The PKAC utilizes the protected kernel RAM for input, output and intermediate variable storage. It may only be accessed from the secure kernel mode. Since public key computations typically take many milliseconds to complete, they may be preempted using a DSP interrupt. Most application interaction with the public key accelerator will occur via the CGX software interface (see the Command Interface section). Both high level public key operations such as RSA Sign or Create Diffie-Hellman Key, as well as primitive operations such as Multiply Vector, Add Long Vector, etc., are presented via the CGX interface. PCI/Cardbus Interface The random number generator is designed to provide highly random, nondeterministic binary numbers at a high delivery rate with little software intervention. The random numbers are accessible to the kernel firmware in a 16-bit register that may be read by the DSP in kernel mode. Once the register is read, the RNG immediately generates a new 16-bit value that is available within 12 microseconds. All application-level access to random numbers should occur through the Kernels CGX_RANDOM command (see the Command Summary section). The random number generator is designed using a "shot noise" true entropy source which is sampled by the master 40 MHz clock of the ADSP-2141L. The entropy source then feeds a complex nonlinear combinatorial circuit that produces the final RNG output based on the interaction of the entropy source and the 40 MHz system clock. Over 200 stages of Linear Feedback Shift Register (LFSR) are incorporated into the RNG design. In order to facilitate FIPS 140-1 compliance, an option may be selected during CGX kernel initialization to enable an ANSI X9.17 Annex C post-randomizer to be applied to the output of the RNG. This randomizer applies the DES ECB algorithm multiple times to further disperse and whiten the random source. Although this is not necessary to ensure the quality of the random numbers, it meets the criteria for a NIST-approved random number generation algorithm. Public Key Accelerator (PKAC) The ADSP-2141L appears as a target on the PCI Bus as a single contiguous memory space of 128k bytes. In this memory space, the host can access the following: * The unprotected internal crypto registers of the ADSP-2141L * IDMA access to the DSP's internal program memory (PM) and data memory (DM) * Paged access to external memory connected to the ADSP-2141L * The Kernel RAM (KRAM) if it has been unprotected by an extended mode program As a PCI Master, the ADSP-2141L can transfer data between: * The unprotected internal crypto registers and FIFOs of the ADSP-2141L and PCI Host memory * External memory and PCI Host memory A 32-bit DMA engine within the ADSP-2141L facilitates these transfers and permits full PCI bandwidth use. Serial EEPROM Interface The serial EEPROM interface allows the ADSP-2141L to automatically read the PCI configuration parameters at chip power-up. IRE can provide the data content for the EEPROM to properly set the chip device vendor ID, type and properties for full compliance with the PCI Plug and Play standards. In addition to being used for storage of host bus parameters, any extra space in the EEPROM may be accessed by the DSP, either in user mode or kernel mode. Support for this function is not included in the standard CGX command set. Refer to the ADSP-2141 User's Manual for the information on the data contents of the EEPROM. Refer to http://www.analog.com/ industry/dsp/ire.html. The public key arithmetic coprocessor (otherwise known as a BigNum processor) is designed to support long vector calculations of the kind needed to perform RSA, Diffie-Hellman and Elliptic Curve operations. The PKAC can perform multiplication, squaring, addition and subtraction on arbitrary length bit vectors. The CGX software is responsible for setting the address register for the operands and Table I. Interrupt Sources Internal Interrupt Sources Interrupt Notes External Interrupt Sources Interrupt IRQ2 IRQL1 IRQL0 IRQE IRQ1 IRQ0 Notes Edge- or Level-Sensitive Level-Sensitive Level-Sensitive Edge-Sensitive Edge- or Level-Sensitive Edge- or Level-Sensitive Reset or Power-Up (PUCR = 1) Power-Down SPORT0 Transmit SPORT0 Receive BDMA Interrupt SPORT1 Transmit Mixed with IRQ1 SPORT1 Receive Mixed with IRQ0 Timer REV. 0 -7- ADSP-2141L Interrupt Controller The DSP core of the ADSP-2141L provides a powerful set of interrupt sources. A total of 14 interrupt sources are available, although two pairs are multiplexed, yielding 12 simultaneous sources. Refer to Table I. The ADSP-2141L enhances the existing interrupt controller within the ADSP-218x DSP Core with some additional functions related to the crypto functional blocks and the external host bus interfaces. Two additional interrupt controller subsystems have been added to the basic interrupt controller as shown in Figure 5. The DSP interrupt controller allows programming between one and nine sources for the IRQ2 interrupt to the DSP. The DIMASK register provides the mask to select which interrupt source is enabled. A pair of status registers, DUMSTAT and DMSTAT, allow the DSP firmware to read the status of any interrupt source either before or after the mask is applied. The host interrupt controller allows programming between one and five sources for the PF7/INT_H interrupt output signal (which may be connected to the interrupt input of the host system). The HMASK register provides the mask to select which interrupt source is enabled. A pair of status registers, HUMSTAT and HMSTAT, allow the host firmware to read the status of any interrupt source either before or after the mask is applied. Laser Variable Storage * 48-Bit Program Control Data (enables/disables various features and configures the ADSP-2141L) * CRC of the Laser Data (to verify integrity of the laser bits) The LSV is a unique triple DES master key-encrypting key that allows the ADSP-2141L to securely store data (primarily other keys) off-chip for later reloading. This is necessary if more storage space is needed than is available with on-chip RAM, or if keys need to be saved and restored after a power outage. Each ADSP-2141L produced is programmed with a unique, randomly generated local storage variable. The internal seed variable is used to randomly initialize the RNG circuits before the entropy is mixed in. Each ADSP-2141L produced is programmed with a unique, randomly generated internal seed variable which is loaded into the RNG at chip boot time and cannot ever be read by software. The 48 Program Control Data Bits (PCDBs) include configuration for permitted key lengths, algorithm enables, red KEK loading, internal IC pulse timing characteristics. The PCDBs provide configuration data that falls into three categories: * Internal IC pulse-timing characteristics * ADSP-2141L hardware version number field * ADSP-2141L feature enables The first two categories consist of data that cannot be altered once the ADSP-2141L has been fabricated. The feature enables can be overridden using a factory token enabler which may be passed to the CGX kernel as part of the CGX_INIT command. This token is digitally signed with an IRE private key and verified internal to the ADSP-2141L with its public key. The CGX_INIT command is documented in the ADSP-2141 CGX Interface Programmer's Guide (available from http://www.ire-ma.com/proddoc.htm). The laser variables are configured through 256 Fuses in the ADSP-2141L, which are programmed during IC manufacture. Each ADSP-2141L produced is programmed with a unique set of Laser Variables. * Local Storage Variable (LSV--the Master Key-Encryption-Key) * Internal Seed Variable DSP DSP INTERRUPT CONTROLLER DICFG DICLR DIFRC HOST INTERRUPT CONTROLLER HICFG HICLR HIFRC HIMASK INTERNAL INTERRUPTS RESET POWER DOWN SPORT0 Tx SPORT0 Rx BDMA INT TIMER INT SPORT1 Tx SPORT1 Rx DSP MASKED STATUS REGISTER ICNTL IMASK IFC DSP UNMASKED STATUS REGISTER H/E CONTEXT0 DONE HOST WROTE CMD DMA xFER DONE DMA xFER QUEUED EXT MEM CONFLICT HASH/ENC ERROR IRQ2 H/E CONTEXT1 DONE H/E CONTEXT0 DONE DSP WROTE CMD HOST MASKED STATUS REGISTER H/E CONTEXT1 DONE HOST UNMASKED STATUS REGISTER ADSP-2183 INTERRUPT CONTROLLER DIMASK HOST INTERRUPT DSP INTERRUPT IRQ2 INTH TO HOST EXTERNAL INTERRUPTS IRQE IRQL0 IRQL1 IRQ0 IRQ1 IRQ2 CRYPTO INTERRUPT SUBSYSTEM BOUNDRY HASH/ENC ERROR Figure 5. Interrupt Controller Block Diagram -8- REV. 0 ADSP-2141L PIN FUNCTIONS I/O Descriptions This section describes the physical I/O hardware on the ADSP-2141L. PIN FUNCTION DESCRIPTIONS-I/O Hardware Pin Name # of Pins Input/ Output O I/O Function Address Output Pins for Program, Data, Byte and I/O Spaces (13 Bits 2183, 13 Bits from Overlay Register) Note: A0 not used for 32-bit memory. Data I/O Pins for Program and Data Memory Spaces D31:0 are used for wide-bus data memory. D23:0 are used for DSP Program RAM. D23:8 are used for I/O Space. D23:8 are used for DSP Data RAM. D15:8 are used for byte memory. D23:16 are also used as Byte Space Addresses Edge- or Level-Sensitive Interrupt Request Level-Sensitive Interrupt Requests Level-Sensitive Interrupt Requests Edge-Sensitive Interrupt Request Bus Request Input Bus Grant Output Bus Grant Hung Output Program Memory Select Output Data Memory Select Output (Lower 16 Bits for 32-Bit DM) Upper Memory Select Output (Upper 16 Bits for 32-Bit DM, Not Used for 16-Bit DM) Byte Memory Select Output I/O Space Memory Select Output Combined Memory Select Output (PMS, DMS*, IOMS, BMS) Memory Read Enable Output Memory Write Enable Output Memory Map Select Input (1 = Overlay External at 0x0000) Boot Option Control Input (0 = BDMA, 1 = IDMA) Clock or Quartz Crystal Input (1/2 of the ADSP-2141 Clock) Processor Clock Output External Memory Bus Address [25:0] 26 Data [31:0] 32 Interrupts IRQ2 IRQL0 IRQL1 IRQE Bus Signals BR BG BGH PMS DMSL DMSH BMS IOMS CMS RD WR Miscellaneous MMAP BMODE CLKIN, XTAL CLKOUT Serial Ports SPORT0 SCLK0 DR0 RFS0 DT0 TFS0 SPORT1 Port Configuration (System Control Reg) -> SCLK1 DR1 RFS1 DT1 TFS1 Power-Down PWD PWDACK REV. 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 I I I I I O O O O O O O O O O I I I O 1 1 1 1 1 I/O I I/O O I/O Serial Port 0 Clock Serial Port 0 Receive Data Input Serial Port 0 Receive Frame Sync Serial Port 0 Transmit Data Output Serial Port 0 Transmit Frame Sync 1 1 1 1 1 1 1 I/O I I/O O I/O I O 1 = Serial Port Serial Port 1 Serial Port 1 Receive Data Input Serial Port 1 Receive Frame Sync Serial Port 1 Transmit Data Output Serial Port 1 Transmit Frame Sync Power-Down Initiate Control Power-Down Acknowledge -9- 0 = Other Clock Flag In IRQ0 Flag Out IRQ1 ADSP-2141L Pin Name Flags PF6:0 PF7/INT_H Emulator EE EBR EBG ERESET EMS EINT ECLK ELIN ELOUT Serial EEPROM Interface EE_DI EE_DO EE_CS EE_SK Bus Select BUS_MODE BUS_SEL PCI Bus (Dedicated Pins) PCI_CLK PCI_PAR PCI_IRDY PCI_STOP Bus Mode Descriptions # of Pins 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Input/ Output I/O I/O Function Programmable I/O Pins Programmable I/O Pin-or-Interrupt Output (Host Mode) (Emulator Only) (Emulator Only) (Emulator Only) (Emulator Only) (Emulator Only) (Emulator Only) (Emulator Only) (Emulator Only) (Emulator Only) O I O O I I I I/O I/O I/O Serial EEPROM Data In Serial EEPROM Data Out Serial EEPROM Chip Select Serial EEPROM Clock Processor Bus Select Bus Select PCI Clock PCI Parity Bit PCI Initiator Ready PCI Abort Transfer *When DMS is enabled for generation of CMS, the CMS is activated for DSP access to external memory only, NOT for DMA controller accesses. The Pin Function Descriptions, Bus Mode table, shows the multiplexed pins in 2183 and PCI mode. For more information on the PCI pins MPLX1-MPLX12, see the Pin Functions Description-PCI Mode Multiplex Bus table on the following page. PIN FUNCTION DESCRIPTIONS--Bus Mode Bus Mode MPLX_RESET MPLX1 MPLX2 MPLX3 MPLX4 MPLX5 MPLX6 MPLX7 MPLX8 MPLX9 MPLX10 MPLX11 MPLX12 MPLX_BUS[31:0] Power GND VDD Total: # of Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 32 Input/ Output I I/O I/O I/O I/O I I I/O I/O I/O I/O I/O O I/O 2183 Mode (bus_mode = 0, bus_sel = 0) RESET_1 PCI Mode (bus_mode = 1, bus_sel = 0) Pci_rst Pci_cbe3 Pci_cbe2 Pci_cbe1 Pci_cbe0 Pci_idsel Pci_gnt Pci_frame Pci_devsel Pci_trdy Pci_perr Pci_serr Pci_req Pci_ad15:0 Pci_ad31:16 IRD IWR IS IAL IACK FL0 FL1 FL2 IAD15:0 N/C 31:16 24 22 208 - Ground Pins - Power Supply Pins (3.3 V) Includes the pins from this table and the I/O Hardware Pin Function Description table. -10- REV. 0 ADSP-2141L IDMA Mode Multiplex Bus Pin Definition IDMA Port (218x Mode) PIN FUNCTION DESCRIPTIONS--IDMA Mode Multiplex Bus Pin Name MPLX5 MPLX6 MPLX7 MPLX8 MPLX9 MPLX10 MPLX11 MPLX12 MPLX_BUS PCI Port IDMA Name IRD IWR IS IAL IACK FL0 FL1 FL2 IAD Pins 1 1 1 1 1 1 1 1 16 I/O I I I I O O O O I/O Description IDMA Port Read Input IDMA Port Write Input IDMA Port Select IDMA Port Address Latch IDMA Port Access Ready Acknowledge Output Flags Output Flags Output Flags IDMA Data I/O PIN FUNCTION DESCRIPTIONS--PCI Mode Multiplex Bus Pin Name MPLX1 MPLX2 MPLX3 MPLX4 MPLX5 MPLX6 MPLX7 MPLX8 MPLX9 MPLX10 MPLX11 MPLX12 MPLX_BUS PF7/INT_H SYSTEM INTERFACE PCI Name Pci_cbe3 Pci_cbe2 Pci_cbe1 Pci_cbe0 Pci_idsel Pci_gnt Pci_frame Pci_devsel Pci_trdy Pci_perr Pci_serr Pci_req Pci_ad15:0 Pci_ad31:16 Pci_intA Pins 1 1 1 1 1 1 1 1 1 1 1 1 32 1 I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O O I/O O Description Bus Command / Byte Enable 3 Bus Command / Byte Enable 2 Bus Command / Byte Enable 1 Bus Command / Byte Enable 0 Initialization Device Select Bus Grant Cycle Frame Device Select Target Ready Parity Error System Error PCI Bus Request PCI Address/Data Bus PCI Interrupt A Request The ADSP-2141L may be integrated into a wide variety of systems, including those that already have a microprocessor and those that will use the ADSP-2141L as the main processor. The device can be configured into one of two Host Bus modes: IDMA or PCI. IDMA Bus Mode specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. The IDMA port access occurs in two phases. The first is the IDMA address latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location; the destination type specifies whether it is a DM or PM access. The falling edge of the address latch signal latches this value to the IDMAA register. Once the address is stored, data can either be read from or written to the ADSP-2141L's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-2141L that a particular transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes an additional processor cycle. Once an access has occurred, the latched address is automatically incremented and another access can occur. Through the IDMAA register, the ADSP-2141L can also specify the starting address and data format for DMA operation. Figure 6 illustrates a typical system configuration for the IDMA mode. -11- The IDMA bus mode operates the same as in a native ADSP218x device, as described in this section. The IDMA port provides an efficient means of communication between a host system and the ADSP-2141L. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP's memorymapped control registers. The IDMA port has a 16-bit multiplexed address and data bus, and supports reading or writing 16-bit data (DM) or 24-bit program memory (PM). The IDMA port is completely asynchronous and can be written to while the ADSP-2141L is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by REV. 0 ADSP-2141L EXTERNAL MEMORY BUS ADSP-2141 CLKOUT 1/2X CLOCK OR CRYSTAL CLKIN XTAL FL0-2 PF0-7 INTERRUPT SOURCES IRQ2 IRQE IRQL0 IRQL1 DATA 31-0 BMS ADDR25-0 26 A13-0 D23-16 A0-A21 BYTE MEMORY (BOOT LOADER) 32 D15-8 DATA CS A10-0 ADDR D23-8 DATA SPORT1 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI IOMS A25-0 CS ADDR D23-0 DATA 16-BIT I/O SPACE 2048 LOCATIONS PROGRAM OVERLAY MEMORY PMS CMS (OPTIONAL) 8192 8K 24 PM SEGMENTS A25-0* D15-0 D31-16 SPORT0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 DATA OVERLAY MEMORY IDMA PORT SYSTEM INTERFACE OR CONTROLLER 16 16 IRD IWR IS IAL IACK IAD15-0 MPLX31-16 RESET PCI_CLK PCI_PAR PCI_IRDY PCI_STOP DMSH DMSL 8192 8K 16 SEGMENTS UP TO 32M 32 BR BG BGH PWD PWDACK BUS_MODE BUS_SEL MMAP BMODE EE_DI EE_DO EE_CS EE_SK BUS ARBITER NC VDD NC VDD OR GND EEPROM NC *ADDR0 FROM THE ADSP-2141 IS NO CONNECT FOR 32-BIT MEMORY. ADSP-2141 ADDR1 IS WIRED TO RAM A0. Figure 6. ADSP-2141L IDMA System Configuration -12- REV. 0 ADSP-2141L PCI Bus Mode Figure 7 illustrates a typical system configuration for the PCI mode. EXTERNAL MEMORY BUS ADSP-2141 CLKOUT 1/2X CLOCK OR CRYSTAL CLKIN XTAL DATA 31-0 PF0-6 IRQ2 IRQE IRQL0 IRQL1 BMS ADDR25-0 26 A13-0 D23-16 A0-A21 BYTE MEMORY (BOOT LOADER) 32 D15-8 DATA CS A10-0 ADDR D23-8 DATA INTERRUPT SOURCES SPORT1 SERIAL DEVICE SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI IOMS A25-0 CS ADDR D23-0 DATA 16-BIT I/O SPACE 2048 LOCATIONS PROGRAM OVERLAY MEMORY PMS CMS (OPTIONAL) 8192 8K 24 PM SEGMENTS A25-0* D15-0 D31-16 SPORT0 SERIAL DEVICE SCLK0 RFS0 TFS0 DT0 DR0 4 DATA OVERLAY MEMORY PCI PORT PCI_CBE3-0 PCI_IDSEL PCI_REQ PCI_GNT PCI_FRAME PCI_DEVSEL PCI_TRDY PCI_PERR PCI_SERR PCI_AD31-0 PCI_RST PCI_CLK PCI_PAR PCI_IRDY PCI_STOP PF7/INT_H DMSH DMSL 8192 8K 16 SEGMENTS UP TO 32M 32 PCI BUS 32 BR BG BGH PWD PWDACK BUS ARBITER VDD BUS_MODE BUS_SEL *ADDR0 FROM THE ADSP-2141 IS NO CONNECT FOR 32-BIT MEMORY. ADSP-2141 ADDR1 IS WIRED TO RAM A0. VDD OR GND INTA MMAP BMODE EEPROM EE_DI EE_DO EE_CS EE_SK SERIAL EEPROM Figure 7. ADSP-2141L PCI System Configuration REV. 0 -13- ADSP-2141L DEVICE OPERATION OPERATIONAL MODES Security Modes Table III. Boot Mode Selection Boot Mode Pins Byte-Wide (BDMA) Boot Mode Host Bus (IDMA) Boot Mode External Program Boot Mode BMODE 0 1 0 MMAP 0 0 1 The ADSP-2141L operates in one of two security modes: kernel mode or user mode. The mode switching is performed on the fly as program execution proceeds. Kernel mode is entered via a jump or call to address 0x2000 with PMOVLAY set to 0x000F. Kernel mode will exit on its own once it has completed a requested operation (or terminates due to an error). Special interrupt handling is performed if the DSP is executing in kernel mode. While executing a CGX command in kernel mode, it is possible to interrupt to a nonprotected vector location and then invoke the kernel again during the interrupt handler. The [IF CONDITION] RTI instruction must be used to return to the kernel from the interrupt handler. The return address and PMOVLAY page must match the interrupted address and PMOVLAY page. If not, the violation reset logic will be triggered. Only one level of kernel mode nesting is permitted. An interrupt to a nonprotected vector location while in nested kernel mode will also trigger the violation reset logic. While in kernel mode, it is possible to interrupt to a protected vector location. In this case, the processor remains in kernel mode. The [IF CONDITION] RTI instruction must be used to return the processor from the interrupt handler. There is no imposed limit on the number of nested interrupts to a protected vector location. Bus Modes The hardware pin states are not relevant after the ADSP-2141L comes out of power-up reset. Refer to the ADSP-2141L User's Manual (available from IRE) for information on BDMA, IDMA and external program boot modes. COMMAND INTERFACE This section provides a general overview of the software command interface to the crypto functions in the ADSP-2141L. Refer to the ADSP-2141 CGX Interface Programmer's Guide (available from http://www.ire-ma.com/proddoc.htm) for more details. Overview The ADSP-2141L provides an embedded crypto library that provides a command interface API (Application Programming Interface) to outside applications. These commands are referred to as CGX (CryptoGraphic eXtensions). The CGX API simultaneously enforces certain security policies within the ADSP-2141L and insulates applications from the details of many complex cryptographic operations. The security policy built into the ADSP-2141L has some of the following rules: * Unencrypted (red) keys may never be retrieved from the ADSP-2141L. * Keys within the ADSP-2141L are marked with an attributes field that specifies key type and trust level. * A key's type field must match the use in a requested operation (i.e., cannot use a KEK to encrypt traffic). * Keys generated internal to the ADSP-2141L (i.e., from RNG) are marked as trusted. * Keys that are negotiated or imported from outside systems are marked untrusted (although they may still be quite secure). * Separate trusted and untrusted key hierarchies may be maintained and customer applications may choose which trust level is required for a given command. For most key management operations, the CGX interface must be used. However, for certain high performance encryption/ hashing applications, the CGX interface may be bypassed and either the DSP or a host processor may exercise direct control over the hash/encrypt block. The ADSP-2141L Host Bus may be configured for one of two personalities: IDMA Mode or PCI Bus Mode. The selection of mode is made with two hardware control inputs BUS_MODE and BUS_SEL at boot time. Table II. Bus Mode Selection Bus Mode Pins IDMA Mode PCI Bus Mode BUS_MODE 0 1 BUS_SEL 0 0 This selection may not be changed after the ADSP-2141L comes out of power-up reset. It is typically expected that the bus mode signals are tied to ground or VDD on the PC Board. Boot Modes The ADSP-2141L may be bootstrap-loaded from one of three sources: byte-wide memory, host processor bus, or external program memory. The selection of mode is made with two hardware control inputs BMODE and MMAP. When the host processor boot mode is selected, any one of the two bus modes may be used. -14- REV. 0 ADSP-2141L COMMAND SUMMARY Approximately 40 CGX Commands are supported in the API to the ADSP-2141L. General Utilities INIT DEFAULT RANDOM GET CHIPINFO SELF TEST Symmetrical Key Management Initializes Secure Kernel and Allow Reconfiguration of the ADSP-2141L Restores Factory Default Settings Generates Random Numbers (between 1K and 64K bytes) Returns ADSP-2141L System Information Runs a suite of self-tests on the hardware and CGX Loads and Decrypts a Secret Key Generates a Secret Key Generates an Internal Key Encryption Key Generates a Key Recovery Key Encryption Key Saves a key protected by the Recovery Key (RKEK) Imports a Red (plaintext) User Secret Key Derives a Secret Key from a Pass Phrase Transforms a Secret Key using IPsec Removes Secret Key from the KCR Exports an IRE-format Secret Key Imports an IRE-format Secret Key Encrypts Data Decrypts Data Loads Secret Key into HW/SW Key Generator Initializes the Hash Operator Hash Customer Data Hash and Encrypt Customer Data Hash and Decrypt Customer Data Combines two secret keys into one key Combines two secret keys into a data string (long key) Creates a secret key from a data string (long key) Hash multiple data items using HMAC Completes the above HMAC and create secret key Generates a Public Keyset (Public and Private Parts) Generates a part of a Public Keyset Generates a Diffie-Hellman Derived Secret Key Exports an IRE-format Public Key Imports an IRE-format Public Key Encrypts Data using RSA Public Key Decrypts Data using RSA Public Key Digitally Signs a Message Verifies a Digital Signature Performs a Vector Add Operation Performs a Vector Subtract Operation Performs a Vector Multiply Operation Performs a Vector Exponentiate Operation Performs a Vector Right or Left Shift Operation Loads/Enables Extended (Downloaded) Algorithm Block Executes Extended (Downloaded) Algorithm Block UNCOVER KEY GEN KEY GEN KEK GEN RKEK SAVE KEY LOAD KEY DERIVE KEY TRANSFORM KEY DESTROY KEY EXPORT KEY IMPORT KEY Symmetrical Encryption ENCRYPT DECRYPT LOAD KG Hash HASH INIT HASH DATA HASH ENCRYPT HASH DECRYPT PRF Functions MERGE KEY MERGE LONG KEY EXTRACT LONG KEY PRF DATA PRF KEY Asymmetrical Key Management GEN PUBKEY GEN NEWPUBKEY GEN NEGKEY EXPORT PUBKEY IMPORT PUBKEY Asymmetrical Encryption PUBKEY ENCRYPT PUBKEY DECRYPT Digital Signatures SIGN VERIFY Math Utilities ADD VECTOR SUB VECTOR MULT VECTOR EXP VECTOR SHIFT VECTOR Extended Mode LOAD EXTENDED EXECUTE EXTENDED REV. 0 -15- ADSP-2141L ABSOLUTE MAXIMUM RATINGS Frequency Dependency For Timing Specifications Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Operating Temperature Range (Ambient) . . . . . 0C to 70C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (5 sec) MQFP . . . . . . . . . . . . . . . . . 280C tCK is defined as 0.5tCKI. The ADSP-2141L uses an input clock with a frequency equal to half the instruction rate: a 20.0 MHz input clock (which is equivalent to 50 ns) yields a 25 ns processor cycle (equivalent to 40 MHz). tCK values within the range of 0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5tCK - 7 ns = 0.5 (25 ns) - 7 ns = 8 ns CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2141L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -16- REV. 0 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade Parameter VDD TAMB Supply Voltage Ambient Operating Temperature Min 3.0 0 ADSP-2141L Max 3.6 70 Unit V C ELECTRICAL CHARACTERISTICS DC SPECIFICATIONS Parameter VIH VIH VIL VOH Hi-Level Input Voltage1, 2 Hi-Level CLKIN/Reset Voltage Lo-Level Input Voltage1, 3 Hi-Level Output Voltage1, 4, 5 Test Conditions @ VDD = max @ VDD = max @ VDD = min @ VDD = min IOH = -0.5 mA @ VDD = min IOH = -100 A6 @ VDD = min IOL = 2 mA @ VDD = max VIN = VDD max 3 @ VDD = max VIN = 0 V @ VDD = max VIN = VDD max8 @ VDD = max VIN = 0 V9 @ VDD = 3.3 TAMB = 25C tCK = 25 ns12 tCK = 30 ns12 @ VDD = 3.3 TAMB = 25C tCK = 25 ns12 tCK = 30 ns12 @ VIN = 2.5 V fIN = 1.0 MHz TAMB = 25C @ VIN = 2.5 V fIN = 1.0 MHz TAMB = 25C Min 2.0 2.4 0.4 2.4 VDD - 0.3 0.4 10 10 10 8 K Grade Typ Max Unit V V V V V V A A A A mA mA VOL IIH IIL IOZH IOZL IDD Lo-Level Output Voltage1, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current9 Supply Current (Idle)10, 11 16 15 IDD Supply Current (Dynamic)11, 13 195 165 mA mA CI CO Input Pin Capacitance3, 6, 14 Output Pin Capacitance6, 7, 14, 15 8 pF 8 pF NOTES 1 Bidirectional pins: D0-D31, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0-15, PF0-PF7. 2 Input only pins: IRQ2, BR, MMAP, BMODE, BUS MODE, BUS SEL, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL. 3 Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, BMODE, BUS MODE, BUS SEL, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL. 4 Output pins: BG, BGH, PMS, DMSL, DMSH, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0-A25, DT0, DT1, CLKOUT, FL2-0. 5 Although specified for TTL outputs, all ADSP-2141L outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Output pins: BG, BGH, PMS, DMSL, BMS, IOMS, DMSH, CMS, RD, WR, IACK, PWDACK, A0-A25, DT0, DT1, CLKOUT, FL2-0, EE_DI, EE_CS, EE_SK. 8 0 V on BR. CLKIN active (to force three-state condition). 9 Three-statable pins: A0-A25, D0-D31, PMS, DMSL, DMSH, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCKL0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0- IAD15, PF0-PF7. 10 Idle refers to ADSP-2141L state of operation during execution of IDLE Instruction. Deasserted pins are driven to either VDD or GND. 11 Current reflects device operating with no output loads. 12 VIN = 0.4 V and 2.4 V. For typical supply currents, refer to Power Dissipation section. 13 IDD measurement taken with 93% of instructions executing from internal memory and 7% from external memory. H/E operations are executing from internal memory concurrently with PCI transactions. Initialization operations are executed from external memory. 14 Applies to MQFP package type. 15 Output pin capacitance is the capacitive load for any three-stated output pin. Specifications subject to change without notice. REV. 0 -17- ADSP-2141L DC SPECIFICATIONS- PCI Bus Pins K Grade Parameter VIH VIL VOH VOL IIH IIL IOZH IOZL CI CCLK CIDSEL LPIN Hi-Level Input Voltage Lo-Level Input Voltage1, 2 Hi-Level Output Voltage1, 3 Lo-Level Output Voltage1, 3 Hi-Level Input Current2 Lo-Level Input Current2 Three-State Leakage Current4 Three-State Leakage Current1 Input Pin Capacitance PCI CLK Pin Capacitance PCI IDSEL Pin Capacitance5 Pin Inductance 1, 2 Test Conditions Min 0.5 VDD -0.5 0.9 VDD Max VDD + 0.5 0.3 VDD 0.1 VDD 10 10 10 10 10 12 8 20 Unit V V V V A A A A pF pF pF nH IOUT = -500 A IOUT = 1500 A 0 < VIN < VDD 0 < VIN < VDD 0 < VIN < VDD 0 < VIN < VDD TAMB = 25C TAMB = 25C TAMB = 25C 5 NOTES 1 Bidirectional pins: MPLX_BUS [31:0}, MPLX1-4, MPLX7-10, MPLX12 2 Input only pins: MPLX_RESET, MPLX5, MPLX6, PCI_CLK, PCI_PAR, PCI_IRDY, PCI_STOP 3 Output only pins: MPLX11 4 Leakage currents include High-Z output leakage for bidirectional buffers with three-state outputs. 5 Lower capacitance of IDSEL (MPLX_5) input-only pin allows for nonresistive connection to Address/Data bus. TIMING PARAMETERS PCI Clock (Guaranteed Over Operating Temperature and Digital Supply Range) The ADSP-2141L is targeted for use in PCI add-on I/O slave card designs. It provides a glueless interface to the PCI bus. All bus drivers are compliant with PCI interface electrical switching and drive capability specifications. The ADSP-2141L does not implement the following signals: LOCK, INTB, INTC, INTD, SBO, SDONE, CLKRUN, AD[64:32], C/BE[7:4], REQ64, ACK64, PAR64. Parameter Timing Requirements: tCYC CLK Cycle Time tHIGH CLK High Time tLOW CLK Low Time CLK Slew Rate1 RST Slew Rate2 Min 25 11 11 1 50 Max 100 Unit ns ns ns V/ns mV/ns 4 NOTES 1 Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the waveform as shown in Figure 8. 2 The minimum RST slew rate applies only to the rising (deassertion) edge of the reset signal, and ensures that system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range. t CYC t HIGH 0.6VCC 0.5VCC 0.4VCC 0.3VCC 0.2VCC t LOW 2V p-p (MINIMUM) Figure 8. Clock Waveform -18- REV. 0 ADSP-2141L Parameter PCI Bus Interface Timing Requirements: CLK to Signal Valid tVAL tON CLK to Low-Z Delay tOFF CLK to High-Z Delay Input Setup to CLK tSU tH Input Hold After CLK tRST-OFF RST Active to Outputs High-Z Min Max Unit 2 2 7 1 11 28 40 ns ns ns ns ns ns CLK VTEST t VAL OUTPUT DELAY VSTEP (3.3V SIGNALING) OUTPUT CURRENT LEAKAGE CURRENT THREE-STATE OUTPUT t ON t OFF VTH CLK VTL t SU VTH tH INPUT VTL VTEST INPUTS VALID VTEST VMAX Figure 9. Output (Top) and Input Timing Measurement Conditions REV. 0 -19- ADSP-2141L Parameter Clock Signals and Reset Timing Requirements: CLKIN Period tCKI tCKIL CLKIN Width Low tCKIH CLKIN Width High Switching Characteristics: tCKL CLKOUT Width Low tCKH CLKOUT Width High tCKOH CLKIN High to CLKOUT High Control Signals Timing Requirement: tRSP RESET Width Low1 Min Max Unit 50 15 15 0.5tCK - 7 0.5tCK - 7 0 100 ns ns ns ns ns ns 20 5tCK ns NOTE 1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). t CKI t CKIH CLKIN t CKIL t CKOH t CKH CLKOUT t CKL Figure 10. Clock Signals and Reset -20- REV. 0 ADSP-2141L Parameter Interrupts and Flags Timing Requirements: IRQx, FI, or PFx Setup Before CLKOUT Low1, 2, 3, 4 tIFS tIFH IRQx, FI, or PFx Hold After CLKOUT High1, 2, 3, 4 Switching Characteristics: tFOH Flag Output Hold After CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low5 Min Max Unit 0.25tCK + 15 0.25tCK 0.5tCK - 7 0.5tCK + 5 ns ns ns ns NOTES 1 If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to the Interrupt Controller Operation section in the Program Control chapter of the ADSP-2100 Family User's Manual for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE. 4 PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag Outputs = PFx, FL0, FL1, FL2, Flag_out. tFOD CLKOUT tFOH FLAG OUTPUTS t IFH IRQx FI PFx t IFS Figure 11. Interrupts and Flags REV. 0 -21- ADSP-2141L Parameter Bus Request/Bus Grant Timing Requirements: BR Hold After CLKOUT High1 tBH tBS BR Setup Before CLKOUT Low1 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable xMS, RD, WR Disable to BG Low tSDB tSE BG High to xMS, RD, WR Enable tSEC xMS, RD, WR Enable to CLKOUT High xMS, RD, WR Disable to BGH Low2 tSDBH tSEH BGH High to xMS, RD, WR Enable2 Min Max Unit 0.25tCK + 2 0.25tCK + 17 ns ns 0.25tCK + 10 ns ns ns ns ns ns 0 0 0.25tCK - 6 0 0 NOTES xMS = PMS, DMSL, DMSH, CMS, IOMS, BMS. 1 BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise, the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User's Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. t BH CLKOUT BR t BS CLKOUT PMS, DMSL, BMS, RD, WR t SD t SEC BG t SDB t SE BGH t SDBH t SEH Figure 12. Bus Request/Bus Grant -22- REV. 0 ADSP-2141L Parameter External Memory Write: ADSP-2141L DMA Initiated Switching Characteristics: tA Clock to Address and DMSx tDW Data Setup Before Write Deasserted Data Hold After Write Deasserted tDH tWP Write Pulsewidth tWDE Write Low to Data Enabled Address, DMSx Setup Before Write Low tASW tDDR Data Disable Before Write/Read Low tCWR Clock High to Write Low Address, DMSx Setup Before Write High tAW tAH Address and DMSx Hold After Clock tWRA Address, DMSx Hold After Write High tWWR Write High to Read/Write Low 1. If wait-state(s) added, then referenced to last wait-state clock interval. 2. w = DMA wait states x tCK. 25ns (REF @ 40MHz) DSP CLOCK OUT Min Max Unit 5 0.5tCK - 2 + w 0.5tCK - 8 0.5tCK - 5 + w -5 1 0 6 0.5tCK - 2 + w 2 0.5tCK - 7 0.5tCK - 3 9 12 ns ns ns ns ns ns ns ns ns ns ns ns t ASW EXT. ADDR (A25-0) t AH tA EXT. DMSH EXT. DMSL t AW t WRA t CWR EXT. WR t WP t WWR t WDE t DW EXT. DATA (D31-0) t DH t DDR Figure 13. External Memory Write: ADSP-2141L DMA Initiated REV. 0 -23- ADSP-2141L Parameter External Memory Read--ADSP-2141L DMA Initiated Timing Requirements: tRDD Read Low to Data Valid tAA Address, DMSx Valid to Data Valid Data Valid Before Read Deasserted tSUR tRDH Data Hold After Read Deasserted Switching Characteristics: tA Clock to Address and DMSx Active Address, DMSx Setup Before Read Low tASR tAH Address and DMSx Hold After Clock tRDA Address, DMSx Hold After Read High Clock High to RD Low tCRD tRP Read Pulsewidth tRWR RD High to Read or Write Low 1. If wait-state(s) added, then referenced to last wait-state clock interval. 2. w = DMA wait states x tCK. 25ns (REF @ 40MHz) DSP CLOCK OUT Min Max Unit 0.5tCK - 8 + w 0.5tCK - 3 + w 4 1 5 2 2 0.5tCK - 7 8 0.5tCK - 5 + w 0.5tCK - 3 9 ns ns ns ns ns ns ns ns ns ns ns 12 tA EXT. ADDR (A25-0) t AH t AA t ASR EXT. DMSH EXT. DMSL t RDA t CRD EXT. RD t RP t RWR t RDD EXT. DATA (D31-0) t SUR t RDH Figure 14. External Memory Read - ADSP-2141L DMA Initiated -24- REV. 0 ADSP-2141L Parameter External Memory Write: ADSP-2141L DSP Initiated Switching Characteristics: Clock to Address, xMS tA tDW Data Setup Before Write Deasserted tDH Data Hold After Write Deasserted Write Pulsewidth tWP tWDE Write Low to Data Enabled tASW Address, xMS Setup Before Write Low Data Disable Before Write/Read Low tDDR tCWR Clock High to Write Low tAW Address, xMS Setup Before Write High Address, xMS Hold After Clock tAH tWRA Address, xMS Hold After Write High tWWR Write High to Read/Write Low 1. If wait-state(s) added, then referenced to last wait-state clock interval. 2. w = DSP wait states x tCK . 25ns (REF @ 40MHz) DSP CLOCK OUT Min Max Unit 1 0.5tCK - 7 + w 0.25tCK - 3.5 0.5tCK - 5 + w 0 0.25tCK - 4 0.25tCK - 4 0.25tCK 0.75tCK - 6 + w 1 0.25tCK - 4 0.5tCK - 5 6 0.5tCK + 9 ns ns ns ns ns ns ns ns ns ns ns ns t ASW t AH EXT. ADDR (A13-0) PMS, DMSx, BMS, IOMS, CMS tA t AW t WRA t CWR EXT. WR t WP t WWR t WDE t DW EXT. DATA (D23-0) t DH t DDR Figure 15. External Memory Write: ADSP-2141L DSP Initiated REV. 0 -25- ADSP-2141L Parameter External Memory Read--ADSP-2141L DSP Initiated Timing Requirements: tRDD Read Low to Data Valid tAA Address, xMS Valid to Data Valid Data Valid Before Read Deasserted tSUR tRDH Data Hold After Read Deasserted Switching Characteristics: tA Clock to Address, xMS Active Address, xMS Setup Before Read Low tASR tAH Address, xMS Hold After Clock tRDA Address, xMS Hold After Read High Clock High to RD Low tCRD tRP Read Pulsewidth tRWR RD High to RD or WR Low 1. If wait-state(s) added, then referenced to last wait-state clock interval. 2. w = DSP wait state x tCK. 25ns (REF @ 40MHz) DSP CLOCK OUT Min Max Unit 0.5tCK - 10 + w 0.75tCK - 11.5 + w 9 0 1 0.25tCK - 4 1 0.25tCK - 3 0.25tCK - 2 0.5tCK - 5 + w 0.5tCK -5 6 ns ns ns ns ns ns ns ns ns ns ns 0.25tCK + 7 tA EXT. ADDR (A13-0) t AH t AA t ASR PMS, DMSx, BMS, IOMS, CMS t RDA t CRD EXT. RD t RP t RWR t RDD EXT. DATA (D23-0) t SUR t RDH Figure 16. External Memory Read - ADSP-2141L DSP Initiated -26- REV. 0 ADSP-2141L Parameter Serial Ports Timing Requirements: tSCK SCLK Period DR/TFS/RFS Setup Before SCLK Low tSCS tSCH DR/TFS/RFS Hold After SCLK Low tSCP SCLKIN Width Switching Characteristics: tCC CLKOUT High to SCLKOUT tSCDE SCLK High to DT Enable tSCDV SCLK High to DT Valid TFS/RFSOUT Hold After SCLK High tRH tRD TFS/RFSOUT Delay from SCLK High tSCDH DT Hold After SCLK High TFS (Alt) to DT Enable tTDE tTDV TFS (Alt) to DT Valid tSCDD SCLK High to DT Disable tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid Min Max Unit 50 4 7 15 0.25tCK 0 0 15 0 0 14 15 15 0.25tCK + 10 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLKOUT t CC t CC t SCK SCLK t SCS DR TFSIN RFSIN t SCH t SCP t SCP t RD t RH RFSOUT TFSOUT t SCDV t SCDE DT t SCDD t SCDH t TDE t TDV TFSOUT ALTERNATE FRAME MODE t RDV RFSOUT MULTICHANNEL MODE FRAME DELAY 0 (MFD = 0) t TDE t TDV TFSIN ALTERNATE FRAME MODE t RDV RFSIN MULTICHANNEL MODE FRAME DELAY 0 (MFD = 0) Figure 17. Serial Ports REV. 0 -27- ADSP-2141L Parameter IDMA Address Latch (IDMA Mode Multiplex Bus) Timing Requirements: tIALP Duration of Address Latch1, 2 MPLX_BUS Address Setup Before Address Latch End2 tIASU tIAH MPLX_BUS Address Hold After Address Latch End2 tIKA MPLX9 Low Before Start of Address Latch2, 3 tIALS Start of Write or Read After Address Latch End2, 3 NOTES 1 Start of Address Latch = MPLX7 Low and MPLX8 High. 2 Start of Write or Read = MPLX7 Low and MPLX6 Low or MPLX5 Low. 3 End of Address Latch = MPLX7 High or MPLX8 Low. Min Max Unit 10 5 3 0 4 ns ns ns ns ns MPLX9 IACK / t IKA MPLX8 IAL / t IALP MPLX7 IS / t IASU MPLX_BUS IAD15-0 t IAH / t IALS MPLX5 OR MPLX6 IRD OR IWR / Figure 18. IDMA Address Latch (IDMA Mode Multiplex Bus) -28- REV. 0 ADSP-2141L Parameter IDMA Write, Short Write Cycle (IDMA Mode, Multiplex Bus) Timing Requirements: tIKW MPLX9 Low Before Start of Write1 Duration of Write1, 2 tIWP tIDSU MPLX_BUS Data Setup Before End of Write2, 3, 4 tIDH MPLX_BUS Hold After End of Write2, 3, 4 Switching Characteristic: tIKHW Start of Write to MPLX9 High NOTES 1 Start of Write = MPLX7 Low and MPLX6 Low. 2 End of Write = MPLX7 High or MPLX6 High. 3 If Write Pulse ends before MPLX9 Low, use specifications t IDSU, tIDH. 4 If Write Pulse ends after MPLX9 Low, use specifications t IKSU, tIKH. t IKW MPLX9 IACK Min Max Unit 0 15 5 3 15 ns ns ns ns ns / t IKHW MPLX7 IS / t IWP MPLX6 IWR / t IDH t IDSU MPLX_BUS IAD15-0 / DATA Figure 19. IDMA Write, Short Write Cycle (IDMA Mode, Multiplex Bus) REV. 0 -29- ADSP-2141L Parameter IDMA Write, Long Write Cycle (IDMA Mode, Multiplex Bus) Timing Requirements: tIKW MPLX9 Low Before Start of Write1 MPLX_BUS Data Setup Before MPLX9 Low2, 3, 4 tIKSU tIKH MPLX_BUS Data Hold After MPLX9 Low2, 3, 4 Switching Characteristics: tIKLW Start of Write to MPLX9 Low4 tIKHW Start of Write to MPLX9 High Min Max Unit 0 0.5tCK + 10 2 1.5tCK 15 ns ns ns ns ns NOTES 1 Start of Write = MPLX7 Low and MPLX6 Low. 2 If Write Pulse ends before MPLX9 Low, use specifications t IDSU, tIDH. 3 If Write Pulse ends after MPLX9 Low, use specifications t IKSU, tIKH. 4 This is the earliest time for MPLX9 Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User's Manual. t IKW MPLX9 IACK / t IKHW t IKLW MPLX7 IS / MPLX6 IWR / t IKSU MPLX_BUS IAD15-0 t IKH DATA / Figure 20. IDMA Write, Long Write Cycle (IDMA Mode, Multiplex Bus) -30- REV. 0 ADSP-2141L Parameter IDMA Read, Long Read Cycle (IDMA Mode, Multiplex Bus) Timing Requirements: tIKR MPLX9 Low Before Start of Read1 Duration of Read1 tIRP Switching Characteristics: tIKHR MPLX9 High After Start of Read1 tIKDS MPLX_BUS Data Setup Before MPLX9 Low MPLX_BUS Data Hold After End of Read2 tIKDH tIKDD MPLX_BUS Data Disabled After End of Read2 tIRDE MPLX_BUS Previous Data Enabled After Start of Read MPLX_BUS Previous Data Valid After Start of Read tIRDV tIRDH1 MPLX_BUS Previous Data Hold After Start of Read (DM/PM1)3 tIRDH2 MPLX_BUS Previous Data Hold After Start of Read (PM2)4 NOTES 1 Start of Read = MPLX7 Low and MPLX5 Low. 2 End of Read = MPLX7 High or MPLX5 High. 3 DM read or first half of PM read. 4 Second half of PM read. Min Max Unit 0 15 15 0.5tCK - 7 0 14 0 15 2tCK - 5 tCK - 5 ns ns ns ns ns ns ns ns ns ns MPLX9 IACK / t IKR MPLX7 IS t IKHR / t IRP MPLX6 IRD / t IRDE MPLX_BUS IAD15-0 t IKDS PREVIOUS DATA READ DATA t IKDH / t IRDV t IRDH t IKDD Figure 21. IDMA Read, Long Read Cycle (IDMA Mode, Multiplex Bus) REV. 0 -31- ADSP-2141L Parameter IDMA Read, Short Read Cycle (IDMA Mode, Multiplex Bus) Timing Requirements: MPLX9 Low Before Start of Read1 tIKR tIRP Duration of Read Switching Characteristics: tIKHR MPLX9 High After Start of Read1 MPLX_BUS Data Hold After End of Read2 tIKDH tIKDD MPLX_BUS Data Disabled After End of Read2 tIRDE MPLX_BUS Previous Data Enabled After Start of Read tIRDV MPLX_BUS Previous Data Valid After Start of Read NOTES 1 Start of Read = MPLX7 Low and MPLX5 Low. 2 End of Read = MPLX7 High or MPLX5 High. Min Max Unit 0 15 15 0 14 0 15 ns ns ns ns ns ns ns MPLX9/IACK t IKR t IKHR MPLX7/IS t IRP MPLX6/IRD t IRDE PREVIOUS DATA t IKDH MPLX_BUS/IAD15-0 t IRDV t IKDD Figure 22. IDMA Read, Short Read Cycle (IDMA Mode, Multiplex Bus) -32- REV. 0 ADSP-2141L CAPACITIVE LOADING Figures 23 and 24 show the capacitive loading characteristics of the ADSP-2141L. 18 16 RISE TIME (0.4V - 2.4V) - ns is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. INPUT OR OUTPUT 1.5V 1.5V T = +70 C VDD = 3.0V 14 12 10 8 6 4 2 0 0 50 100 150 CL - pF 200 250 300 Figure 25. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Enable Time Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. REFERENCE SIGNAL Figure 23. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) 18 16 14 VALID OUTPUT DELAY OR HOLD - ns tMEASURED tENA VOH (MEASURED) OUTPUT VOL (MEASURED) tDIS VOH (MEASURED) - 0.5V VOL (MEASURED) +0.5V 2.0V 1.0V VOH (MEASURED) 12 10 8 6 4 2 tDECAY OUTPUT STOPS DRIVING VOL (MEASURED) OUTPUT STARTS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. NOMINAL -2 -4 0 50 100 CL - pF 150 200 250 Figure 26. Output Enable/Disable IOL Figure 24. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) TEST CONDITIONS Output Disable Time TO OUTPUT PIN +1.5V 50pF Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: t DECAY = CL * 0.5V iL IOH Figure 27. Equivalent Device Loading for AC Measurements (Including All Fixtures) from which t DIS = t MEASURED - t DECAY REV. 0 -33- ADSP-2141L Table IV. Thermal Ratings: MQFP Package Rating Description Thermal Resistance (Case to Ambient) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Symbol CA JA JC Value (MQFP Still Air) 30.7C/W 35C/W 4.3C/W Value (MQFP 9500 fpm) 16.7C/W 21C/W 4.3C/W ENVIRONMENTAL CONDITIONS POWER DISSIPATION The following figures assume a four-layer JEDEC printed circuit board: TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C OUTPUT DRIVE CURRENTS Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation depends on the sequence in which instructions execute and the data operands involved. See IDDIN calculation in Electrical Characteristics section. Internal power dissipation is calculated this way: PINT = IDDIN x VDD The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: - - - - the number of output pins that switch during each cycle (O) the maximum frequency at which the pins can switch (f) the load capacitance of the pins (C) the voltage swing of the pins (VDD). PEXT = O x C x VDD2 x f Figures 28 and 29 show typical I-V characteristics for the output drivers of the ADSP-2141L. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 80 60 SOURCE CURRENT - mA VDD = 3.3V @ +25 C VDD = 3.6V @ 0 C The external component is calculated using: The load capacitance should include the processor's package capacitance (CIN). The frequency f includes driving the load high and then back low. 40 20 VDD = 3.0V @ +70 C 0 -20 -40 -60 -80 -100 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE - V 3.0 3.5 4.0 VDD = 3.0V @ +70 C VDD = 3.3V @ +25 C VDD = 3.6V @ 0 C Figure 28. Typical Drive Currents (PCI Pins) 80 VDD = 3.3V @ +25 C 60 VOH SOURCE CURRENT - mA 40 20 0 VDD = 3.0V @ +70 C -20 VOL -40 -60 VDD = 3.6V @ 0 C -80 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE - V VDD = 3.6V @ 0 C VDD = 3.0V @ +70 C VDD = 3.3V @ +25 C 3.0 3.5 4.0 Figure 29. Typical Drive Currents (Addr/Dbus/rd/wr Pins) -34- REV. 0 ADSP-2141L Example: POWER, INTERNAL 940 POWER (PINT) - mW In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Assumptions: 840 VDD = 3.6V 740 706mW 640 554mW 540 VDD = 3.0V 440 431mW 340 32 823mW * * * * External data memory is accessed every cycle with 50% of the address pins switching. External data memory writes occur every other cycle with 50% of the data pins switching. Each address and data pin has a 10 pF total load at the pin. The application operates at VDD = 3.3 V and tCK = 25 ns. 649mW VDD = 3.3V 509mW Total Power Dissipation = PINT + (C x VDD2 x f ) PINT = internal power dissipation from Power vs. Frequency graphs (Figures 30 and 31). (C x VDD2 x f ) is calculated for each output: # of Pins x C Address, DMS Data Output, WR RD CLKOUT 8 9 1 1 x 10 pF x 10 pF x 10 pF x 10 pF 33 34 35 36 37 38 39 FREQUENCY - MHz 40 41 42 Figure 30. Power vs. Frequency POWER, IDLE 80 x VDD2 x 3.3 V x 3.32 V x 3.32 V x 3.32 V 2 xf x 40 MHz x 20 MHz x 40 MHz x 20 MHz = 34.8 mW = 19.6 mW = 2.2 mW = 4.4 mW 61.0 mW 75 VDD = 3.6V 70 POWER (PIDLE) - mW 74mW 68mW 65 60 55 50 45 41mW 40 32 33 34 51mW Total power dissipation for this example is PINT +61 mW. VDD = 3.3V 53mW VDD = 3.0V 35 36 37 38 39 FREQUENCY - MHz 40 43mW 41 42 Figure 31. Power vs. Frequency REV. 0 -35- ADSP-2141L Pin Configurations For all multiplexed pins the active sense is determined by the mode selected. Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 EMS EE GND ECLK ELOUT ELIN EINT EBR EBG MMAP BMODE BUS_MODE BUS_SEL EE_SK EE_CS EE_DI EE_DO VDD GND PF[7]/INT_H PF[6] PF[5] PF[4] PF[3] PF[2] PF[1] PF[0] PWD PWDACK BR BG BGH IRQE IRQL0 IRQL1 IRQ2 VDD GND MPLX_RESET MPLX12 MPLX_BUS[31] VDD Pin # Pin Name 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PCI_CLK GND MPLX_BUS[30] MPLX_BUS[29] MPLX_BUS[28] MPLX_BUS[27] VDD GND MPLX_BUS[26] MPLX_BUS[25] MPLX_BUS[24] MPLX1 MPLX_BUS[23] MPLX_BUS[22] VDD GND MPLX_BUS[21] MPLX_BUS[20] MPLX_BUS[19] MPLX_BUS[18] GND VDD VDD GND MPLX_BUS[17] MPLX_BUS[16] MPLX2 PCI_IRDY VDD GND PCI_STOP MPLX10 MPLX11 PCI_PAR VDD GND MPLX3 MPLX7 MPLX9 MPLX8 GND VDD Pin # Pin Name 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 VDD GND MPLX6 MPLX5 MPLX_BUS[15] MPLX_BUS[14] MPLX_BUS[13] MPLX_BUS[12] VDD GND MPLX_BUS[11] MPLX_BUS[10] MPLX_BUS[9] MPLX_BUS[8] VDD GND MPLX4 MPLX_BUS[7] MPLX_BUS[6] MPLX_BUS[5] MPLX_BUS[4] VDD GND MPLX_BUS[3] MPLX_BUS[2] MPLX_BUS[1] MPLX_BUS[0] GND CLKOUT VDD GND WR RD DMSH DMSL PMS BMS CMS IOMS VDD CLKIN XTAL Pin # Pin Name 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 164 166 167 168 GND ADDR[0] ADDR[1] ADDR[2] ADDR[3] VDD ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] ADDR[12] ADDR[13] GND ADDR[14] ADDR[15] ADDR[16] ADDR[17] ADDR[18] ADDR[19] VDD ADDR[20] ADDR[21] ADDR[22] ADDR[23] ADDR[24] ADDR[25] DT0 TFS0 RFS0 DR0 SCLK0 DT1 TFS1 RFS1 DR1 SCLK1 GND VDD Pin # 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Name GND DATA[0] DATA[1] DATA[2] DATA[3] VDD GND DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] VDD GND DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] VDD GND DATA[22] DATA[23] DATA[24] DATA[25] DATA[26] DATA[27] DATA[28] DATA[29] DATA[30] DATA[31] ERESET -36- REV. 0 EMS EE GND ECLK ELOUT ELIN EINT EBR EBG MMAP BMODE BUS_MODE BUS_SEL EE_SK EE_CS EE_DI EE_DO VDD GND PF[7]/INT_H PF[6] PF[5] PF[4] PF[3] PF[2] PF[1] PF[0] PWD PWDACK BR BG BGH IRQE IRQL0 IRQL1 IRQ2 VDD GND MPLX_RESET/Pci_rst MPLX12/Pci_req MPLX_BUS/Pci_ad[31] VDD PCI_CLK GND MPLX_BUS/Pci_ad[30] MPLX_BUS/Pci_ad[29] MPLX_BUS/Pci_ad[28] MPLX_BUS/Pci_ad[27] VDD GND MPLX_BUS/Pci_ad[26] MPLX_BUS/Pci_ad[25] REV. 0 8 7 5 6 2 1 3 4 9 48 49 46 47 44 43 42 19 18 17 16 14 15 12 13 11 10 21 22 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 116 WR 115 GND 120 PMS 119 DMSL 118 DMSH 117 RD 138 ADDR[9] 137 ADDR[8] 114 VDD 113 CLKOUT 151 ADDR[20] 150 VDD 148 ADDR[18] 147 ADDR[17] 106 VDD 121 BMS 127 GND 126 XTAL 123 IOMS 122 CMS 125 CLKIN 124 VDD 130 ADDR[2] 129 ADDR[1] 128 ADDR[0] 132 VDD 131 ADDR[3] 134 ADDR[5] 133 ADDR[4] 136 ADDR[7] 135 ADDR[6] 144 ADDR[14] 143 GND 146 ADDR[16] 145 ADDR[15] 149 ADDR[19] 153 ADDR[22] 152 ADDR[21] 156 ADDR[25] 155 ADDR[24] 154 ADDR[23] 142 ADDR[13] 141 ADDR[12] 140 ADDR[11] 139 ADDR[10] 105 MPLX_BUS/Pci_ad[4] 108 MPLX_BUS/Pci_ad[3] 107 GND 112 GND 111 MPLX_BUS/Pci_ad[0] 110 MPLX_BUS/Pci_ad[1] 109 MPLX_BUS/Pci_ad[2] PIN 1 IDENTIFIER 189 GND 188 VDD 187 DATA[15] 186 DATA[14] 185 DATA[13] 184 DATA[12] 183 DATA[11] 182 DATA[10] 181 DATA[9] 180 DATA[8] 179 DATA[7] 178 DATA[6] 177 DATA[5] 176 DATA[4] 175 GND 174 VDD 173 DATA[3] 172 DATA[2] 171 DATA[1] 170 DATA[0] 169 GND 168 VDD 167 GND 166 SCLK1 165 DR1 164 RFS 163 1 FS1 T 162 DT1 161 SCLK0 160 DR0 159 RFS0 158 TFS0 157 DT0 50 51 45 41 39 40 38 37 36 35 34 33 32 29 30 31 28 27 26 25 24 23 20 208 ERESET 207 DATA[31] 206 DATA[30] 205 DATA[29] 204 DATA[28] 203 DATA[27] 202 DATA[26] 201 DATA[25] 200 DATA[24] 199 DATA[23] 198 DATA[22] 197 GND 196 VDD 195 DATA[21] 194 DATA[20] 193 DATA[19] 192 DATA[18] 191 DATA[17] 190 DATA[16] ADSP-2141L OO PINOUT PCI Mode TOP VIEW (Not to Scale) PCI MODE -37- MPLX_BUS/Pci_ad[24] MPLX1/Pci_cbe3 MPLX_BUS/Pci_ad[23] MPLX_BUS/Pci_ad[22] VDD GND MPLX_BUS/Pci_ad[21] MPLX_BUS/Pci_ad[20] MPLX_BUS/Pci_ad[20] MPLX_BUS/Pci_ad[18] GND VDD VDD GND MPLX_BUS/Pci_ad[17] MPLX_BUS/Pci_ad[16] MPLX2/Pci_cbe2 PCI_IRDY VDD GND PCI_STOP MPLX10/Pci_Perr MPLX11/Pci_serr PCI_PAR VDD GND MPLX3/Pci_cbe1 MPLX7/Pci_frame MPLX9/Pci_trdy MPLX8/Pci_devsel GND VDD VDD GND MPLX6/Pci_gnt MPLX5/Pci_idsel MPLX_BUS/Pci_ad[15] MPLX_BUS/Pci_ad[14] MPLX_BUS/Pci_ad[13] MPLX_BUS/Pci_ad[12] VDD GND MPLX_BUS/Pci_ad[11] MPLX_BUS/Pci_ad[10] MPLX_BUS/Pci_ad[9] MPLX_BUS/Pci_ad[8] VDD GND MPLX4/Pci_cbe0 MPLX_BUS/Pci_ad[7] MPLX_BUS/Pci_ad[6] MPLX_BUS/Pci_ad[5] ADSP-2141L ADSP-2141L EMS EE GND ECLK ELOUT ELIN EINT EBR EBG MMAP BMODE BUS_MODE BUS_SEL EE_SK EE_CS EE_DI EE_DO VDD GND PF[7]/INT_H PF[6] PF[5] PF[4] PF[3] PF[2] PF[1] PF[0] PWD PWDACK BR BG BGH IRQE IRQL0 IRQL1 IRQ2 VDD GND MPLX_RESET/RESET_1 MPLX12/FL2 MPLX_BUS/NC[31] VDD PCI_CLK GND MPLX_BUS/NC[30] MPLX_BUS/NC[29] MPLX_BUS/NC[28] MPLX_BUS/NC[27] VDD GND MPLX_BUS/NC[26] MPLX_BUS/NC[25] 3 4 8 7 5 6 2 1 17 9 16 14 15 11 10 12 13 48 49 45 36 47 46 44 43 42 39 40 38 37 35 34 33 32 29 30 31 28 25 24 23 20 19 18 26 27 21 22 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 117 RD 116 WR 127 GND 126 XTAL 121 BMS 120 PMS 123 IOMS 122 CMS 119 DMSL 118 DMSH 125 CLKIN 124 VDD 138 ADDR[9 ] 137 ADDR[8] 130 ADDR[2] 129 ADDR[1] 128 ADDR[0] 115 GND 114 VDD 113 CLKOUT 151 ADDR[20] 150 VDD 152 ADDR[21] 153 ADDR[22] 156 ADDR[25] 155 ADDR[24] 149 ADDR[19] 148 ADDR[18] 106 VDD 131 ADDR[3] 133 ADDR[4] 132 VDD 135 ADDR[6] 134 ADDR[5] 154 ADDR[23] 140 ADDR[11 139 ] DDR[10] A 142 ADDR[13] 141 ADDR[12] 144 ADDR[14] 143 GND 146 ADDR[16] 145 ADDR[15] 147 ADDR[17] 136 ADDR[7] 105 MPLX_BUS/IAD[4] 108 MPLX_BUS/IAD[3] 107 GND 110 MPLX_BUS/IAD[1 109 ] MPLX_BUS/IAD[2] 112 GND 111 MPLX_BUS/IAD[0] PIN 1 IDENTIFIER 208 ERESET 207 DATA[31] 206 DATA[30] 205 DATA[29] 204 DATA[28] 203 DATA[27] 202 DATA[26] 201 DATA[25] 200 DATA[24] 199 DATA[23] 198 DATA[22] 197 GND 196 VDD 195 DATA[21] 194 DATA[20] 193 DATA[19] 192 DATA[18] 191 DATA[17] 190 DATA[16] 189 GND 188 VDD 187 DATA[15] 186 DATA[14] 185 DATA[13] 184 DATA[12] 183 DATA[11] 182 DATA[10] 181 DATA[9] 180 DATA[8] 179 DATA[7] 178 DATA[6] 177 DATA[5] 176 DATA[4] 175 GND 174 VDD 173 DATA[3] 172 DATA[2] 171 DATA[1] 170 DATA[0] 169 GND 168 VDD 167 GND 166 SCLK1 165 DR1 164 RFS1 163 TFS1 162 DT1 161 SCLK0 160 DR0 159 RFS0 158 TFS0 157 DT0 51 50 41 PINOUT 2183-Mode OO ADSP-2141L 2183 MODE TOP VIEW (Not to Scale) -38- MPLX_BUS/NC[24] MPLX1/NC MPLX_BUS/NC[23] MPLX_BUS/NC[22] VDD GND MPLX_BUS/NC[21] MPLX_BUS/NC[20] MPLX_BUS/NC[19] MPLX_BUS/NC[18] GND VDD VDD GND MPLX_BUS/NC[17] MPLX_BUS/NC[16] MPLX2/NC PCI_IRDY VDD GND PCI_STOP MPLX10/FL0 MPLX11/FL1 PCI_PAR VDD GND MPLX3/NC MPLX7/IS MPLX9/IACK MPLX8/IAL GND VDD VDD GND MPLX6/IWR MPLX5/IRD MPLX_BUS/IAD[15] MPLX_BUS/IAD[14] MPLX_BUS/IAD[13] MPLX_BUS/IAD[12] VDD GND MPLX_BUS/IAD[11] MPLX_BUS/IAD[10] MPLX_BUS/IAD[9] MPLX_BUS/IAD[8] VDD GND MPLX4/NC MPLX_BUS/IAD[7] MPLX_BUS/IAD[6] MPLX_BUS/IAD[5] REV. 0 ADSP-2141L PACKAGE DESCRIPTION Package Details The package shown below is a 208-lead metric quad flatpack. Measurements are listed in English and (metric). Because this package is designed as a metric package, Analog Devices recommends that you use these measurements for any PCB layout. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 208-Lead Metric Plastic Quad Flatpack (MQFP) (Nonhermetic) 0.164 (4.10) MAX 0.041 (1.03) 0.035 (0.88) 0.031 (0.78) SEATING PLANE 1.256 (31.40) 1.248 (31.20) SQ 1.240 (31.00) 10 TYP 208 1 157 156 TOP VIEW (PINS DOWN) 1.124 (28.10) 1.120 (28.00) SQ 1.116 (27.90) 0.003 (0.08) MAX LEAD COPLANARITY 0.020 (0.50) 0.010 (0.25) 0.144 (3.59) 0.136 (3.39) 52 53 105 104 0.020 (0.50) BSC LEAD PITCH NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.003 (0.08) FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. THE 208 LEAD MQFP IS A METRIC PACKAGE. ENGLISH DIMENSIONS PROVIDED ARE APPROXIMATE AND MUST NOT BE USED FOR BOARD DESIGN PURPOSES 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) LEAD WIDTH ORDERING GUIDE Part Number ADSP-2141LKS-N1 ADSP-2141LKS-E12 1 Ambient Temperature Range 0C to +70C 0C to +70C Instruction Rate 40 MHz 40 MHz Package Description 208-Lead MQFP 208-Lead MQFP Package Option S-208 S-208 PRINTED IN U.S.A. NOTES 1 The ADSP-2141LKS-N1 is an electrically equivalent, full function, production (non x-grade) version of the product described in this data sheet. (Full function = Triple DES enabled, full 168-bit key length, full 2048-bit public key lengths, red keys allowed.) 2 The ADSP-2141LKS-E1 is an electrically equivalent, full function, production (non x-grade) version of the product d escribed in this data sheet except for the following: Encryption: DES only, with maximum 56-bit key length. Triple DES is disabled. Public Key Algorithms: Public Key Algorithms limited to 1024-bit max modulus. Red keys not allowed in hardware crypto context. REV. 0 -39- C3654-5-1/00 (rev. 0) |
Price & Availability of ADSP-2141L
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |